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tlv5636 2.7 v to 5.5 v low power 12-bit digital-to-analog converter with internal reference and power down slas223 june 1999 1 post office box 655303 ? dallas, texas 75265 features 12-bit voltage output dac programmable internal reference programmable settling time: 1 m s in fast mode, 3.5 m s in slow mode compatible with tms320 and spi ? serial ports differential nonlinearit y... <0.5 lsb typ monotonic over temperature applications digital servo control loops digital offset and gain adjustment industrial process control machine and motion control devices mass storage devices description the tlv5636 is a 12-bit voltage output dac with a flexible 4-wire serial interface. the serial interface allows glueless interface to tms320 and spi ? , qspi ? , and microwire ? serial ports. it is programmed with a 16-bit serial string containing 4 control and 12 data bits. the resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. the programmable settling time of the dac allows the designer to optimize speed vs power dissipation. with its on-chip programmable precision voltage reference, the tlv5636 simplifies overall system design. because of its ability to source up to 1 ma, the reference can also be used as a system reference. implemented with a cmos process, the device is designed for single supply operation from 2.7 v to 5.5 v. it is available in an 8-pin soic and 8-pin msop package to reduce board space in standard commercial and industrial temperature ranges. available options package t a soic (d) msop (dgk) 0 c to 70 c tlv5636cd tlv5636cdgk 40 c to 85 c tlv5636id tlv5636idgk please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. copyright ? 1999, texas instruments incorporated production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. 1 2 3 4 8 7 6 5 din sclk cs fs v dd out ref agnd d or dgk package (top view) spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corporation.
tlv5636 2.7 v to 5.5 v low power 12-bit digital-to-analog converter with internal reference and power down slas223 june 1999 2 post office box 655303 ? dallas, texas 75265 functional block diagram serial interface and control 12-bit dac latch cs din out power-on reset x2 12 2-bit control latch 2 power and speed control 2 voltage bandgap pga with output enable 12 ref fs sclk terminal functions terminal i/o/p description name no. i/o/p description agnd 5 p ground cs 3 i chip select. digital input active low, used to enable/disable inputs din 1 i digital serial data input fs 4 i frame sync input out 7 o dac a analog voltage output ref 6 i/o analog reference voltage input/output sclk 2 i digital serial clock input v dd 8 p positive power supply
tlv5636 2.7 v to 5.5 v low power 12-bit digital-to-analog converter with internal reference and power down slas223 june 1999 3 post office box 655303 ? dallas, texas 75265 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) 2 supply voltage (v dd to agnd) 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . reference input voltage range 0.3 v to v dd + 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . digital input voltage range 0.3 v to v dd + 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating free-air temperature range, t a : tlv5636c 0 c to 70 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . tlv5636i 40 c to 85 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditi onso is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions min nom max unit su pp ly voltage v dd v dd = 5 v 4.5 5 5.5 v s u ppl y v oltage , v dd v dd = 3 v 2.7 3 3.3 v power on reset, por 0.55 2 v high-level digital input voltage, v ih v dd = 2.7 v to 5.5 v 2 v low-level digital input voltage, v il v dd = 2.7 v to 5.5 v 0.8 v reference voltage, v ref to ref terminal v dd = 5 v (see note 1) agnd 2.048 v dd 1.5 v reference voltage, v ref to ref terminal v dd = 3 v (see note 1) agnd 1.024 v dd 1.5 v load resistance, r l 2 k w load capacitance, c l 100 pf clock frequency, f clk 20 mhz o p erating free air tem p erature t a tlv5636c 0 70 c operating free - air temperat u re , t a tlv5636i 40 85 c note 1: due to the x2 output buffer, a reference input voltage (v dd 0.4 v)/2 causes clipping of the transfer function. the output buffer of the internal reference must be disabled, if an external reference is used.
tlv5636 2.7 v to 5.5 v low power 12-bit digital-to-analog converter with internal reference and power down slas223 june 1999 4 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating conditions (unless otherwise noted) power supply parameter test conditions min typ max unit i dd power su pp ly current no load, all in p uts = agnd or v dd fast 2.3 3.3 ma i dd power su ly current all in uts = agnd or v dd , dac latch = 0x800 slow 1.5 1.9 ma power-down supply current see figure 8 0.01 10 m a psrr power su pp ly rejection ratio zero scale, see note 2 65 db psrr po w er s u ppl y rejection ratio full scale, see note 3 65 db notes: 2. power supply rejection ratio at zero scale is measured by varying v dd and is given by: psrr = 20 log [(e zs (v dd max) e zs (v dd min))/v dd max] 3. power supply rejection ratio at full scale is measured by varying v dd and is given by: psrr = 20 log [(e g (v dd max) e g (v dd min))/v dd max] static dac specifications parameter test conditions min typ max unit resolution 12 bits inl integral nonlinearity, end point adjusted see note 4 2 4 lsb dnl differential nonlinearity see note 5 0.5 1 lsb e zs zero-scale error (offset error at zero scale) see note 6 20 mv e zs tc zero-scale-error temperature coefficient see note 7 10 ppm/ c e g gain error see note 8 0.6 % full scale v e g t c gain error temperature coefficient see note 9 10 ppm/ c notes: 4. the relative accuracy or integral nonlinearity (inl) sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors. 5. the differential nonlinearity (dnl) sometimes referred to as differential error, is the difference between the measured and i deal 1 lsb amplitude change of any two adjacent codes. monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. 6. zero-scale error is the deviation from zero voltage output when the digital input code is zero. 7. zero-scale-error temperature coefficient is given by: e zs tc = [e zs (t max ) e zs (t min )]/v ref 10 6 /(t max t min ). 8. gain error is the deviation from the ideal output (2v ref 1 lsb) with an output load of 10 k w excluding the effects of the zero-error. 9. gain temperature coefficient is given by: e g tc = [e g (t max ) e g (t min )]/v ref 10 6 /(t max t min ). output specifications parameter test conditions min typ max unit v o output voltage r l = 10 k w 0 v dd 0.4 v output load regulation accuracy v o = 4.096 v, 2.048 v r l = 2 k w 0.25 % full scale v reference pin configured as output (ref) parameter test conditions min typ max unit v ref(outl) low reference voltage 1.003 1.024 1.045 v v ref(outh) high reference voltage v dd > 4.75 v 2.027 2.048 2.069 v i ref(source) output source current 1 ma i ref(sink) output sink current 1 ma load capacitance 100 pf psrr power supply rejection ratio 65 db
tlv5636 2.7 v to 5.5 v low power 12-bit digital-to-analog converter with internal reference and power down slas223 june 1999 5 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating conditions (unless otherwise noted) (continued) reference pin configured as input (ref) parameter test conditions min typ max unit v i input voltage 0 v dd1.5 v r i input resistance 10 m w c i input capacitance 5 pf reference in p ut bandwidth ref=02v +1024vdc fast 1.3 mhz reference inp u t band w idth ref = 0 . 2 v pp + 1 . 024 v dc slow 525 khz reference feedthrough ref = 1 v pp at 1 khz + 1.024 v dc (see note 10) 80 db note 10: reference feedthrough is measured at the dac output with an input code = 0x000. digital inputs parameter test conditions min typ max unit i ih high-level digital input current v i = v dd 1 m a i il low-level digital input current v i = 0 v 1 m a c i input capacitance 8 pf analog output dynamic performance parameter test conditions min typ max unit t (fs) out p ut settling time full scale r l = 10 k w ,c l = 100 pf, fast 1 3 m s t s(fs) o u tp u t settling time , f u ll scale l , l , see note 11 slow 3.5 7 m s t (cc) out p ut settling time code to code r l = 10 k w ,c l = 100 pf, fast 0.5 1.5 m s t s(cc) o u tp u t settling time , code to code l , l , see note 12 slow 1 2 m s sr slew rate r l = 10 k w ,c l = 100 pf, fast 8 v/ m s sr sle w rate l , l , see note 13 slow 1.5 v/ m s glitch energy din = 0 to 1, f clk = 100 khz, cs = v dd 5 nvs snr signal-to-noise ratio 71 75 s/(n+d) signal-to-noise + distortion f s = 480 ksps, f out = 1 khz, 59 66 db thd total harmonic distortion s , out , r l = 10 k w ,c l = 100 pf 67 59 db spurious free dynamic range 59 69 notes: 11. settling time is the time for the output signal to remain within 0.5 lsb of the final measured value for a digital input code change of 0x020 to 0xfdfand 0xfdf to 0x020 respectively. not tested, assured by design. 12. settling time is the time for the output signal to remain within 0.5 lsb of the final measured value for a digital input code change of one count. not tested, assured by design. 13. slew rate determines the time it takes for a change of the dac output from 10% to 90% full-scale voltage.
tlv5636 2.7 v to 5.5 v low power 12-bit digital-to-analog converter with internal reference and power down slas223 june 1999 6 post office box 655303 ? dallas, texas 75265 digital input timing requirements min nom max unit t su(csfs) setup time, cs low before fs falling edge 10 ns t su(fs-ck) setup time, fs low before first negative sclk edge 8 ns t su(c16-fs) setup time, 16 th negative sclk edge after fs low on which bit d0 is sampled before rising edge of fs 10 ns t su(c16-cs) setup time, 16 th positive sclk edge (first positive after d0 is sampled) before cs rising edge. if fs is used instead of 16 th positive edge to update dac, then setup time between fs rising edge and cs rising edge. 10 ns t wh sclk pulse duration high 25 ns t wl sclk pulse duration low 25 ns t su(d) setup time, data ready before sclk falling edge 8 ns t h(d) hold time, data held valid after sclk falling edge 5 ns t wh(fs) fs pulse duration high 25 ns parameter measurement information t wl sclk cs din fs d15 d14 d13 d12 d1 d0 x x 1 x 2 3 4 5 15 16 x t wh t su(d) t h(d) t su(cs-fs) t wh(fs) t su(fs-ck) t su(c16-fs) t su(c16-cs) figure 1. timing diagram
tlv5636 2.7 v to 5.5 v low power 12-bit digital-to-analog converter with internal reference and power down slas223 june 1999 7 post office box 655303 ? dallas, texas 75265 typical characteristics 2.0685 2.0675 2.067 2.066 0 0.5 1 1.5 2 2.5 3 output voltage v 2.07 2.0705 source current ma output voltage vs load current 2.071 3.5 4 2.0695 2.0698 2.068 2.0665 slow fast v dd = 3 v, ref = int. 1 v, input code = 4095 figure 2 v dd = 5 v, ref = int. 2 v, input code = 4095 4.132 4.131 4.13 4.129 0 0.5 1 1.5 2 2.5 3 output voltage v 4.133 4.134 source current ma output voltage vs load current 4.135 3.5 4 slow fast figure 3 figure 4 v dd = 3 v, ref = int. 1 v, input code = 0 slow fast 1.5 1 0.5 0 0 0.5 1 1.5 2 2.5 3 output voltage v 2 2.5 sink current ma output voltage vs load current 3 3.5 4 v dd = 5 v, ref = int. 2 v, input code = 0 slow fast 3.5 2 1 0 0 0.5 1 1.5 2 2.5 3 output voltage v 4 4.5 sink current ma output voltage vs load current 5 3.5 4 3 2.5 1.5 0.5 figure 5
tlv5636 2.7 v to 5.5 v low power 12-bit digital-to-analog converter with internal reference and power down slas223 june 1999 8 post office box 655303 ? dallas, texas 75265 typical characteristics figure 6 1.5 1 0.5 40 30 20 10 0 20 30 supply current ma 2 2.5 supply current vs temperature 3 40 50 70 90 10 60 80 fast mode slow mode t temperature c v dd = 5 v, ref = 2 v, input code = 4095 figure 7 1.5 1 0.5 403020 10 0 10 20 2 2.5 3 30 40 50 90 60 70 80 supply current ma supply current vs temperature fast mode slow mode t temperature c v dd = 3 v, ref = 1 v, input code = 4095 figure 8 1.4 0.8 0.4 0 0 10203040 power down supply current ma 1.6 1.8 power down supply current vs time 2 50 60 70 80 1.2 1 0.6 0.2 t time m s i dd figure 9 40 50 80 100 100 1000 thd+n total harmonic distortion and noise db 20 10 f frequency hz total harmonic distortion and noise vs frequency 0 10000 100000 30 60 70 90 fast mode slow mode v dd = 5 v v ref = 1 v dc + 1 v p/p sinewave output full scale
tlv5636 2.7 v to 5.5 v low power 12-bit digital-to-analog converter with internal reference and power down slas223 june 1999 9 post office box 655303 ? dallas, texas 75265 typical characteristics 40 50 80 100 100 1000 thd total harmonic distortion db 20 10 f frequency hz total harmonic distortion vs frequency 0 10000 100000 30 60 70 90 fast mode slow mode v dd = 5 v v ref = 1 v dc + 1 v p/p sinewave output full scale figure 10 figure 11 dnl differential nonlinearity lsb digital input code differential nonlinearity vs digital input code 1 0.5 0 0.5 1 0 1024 2048 3072 4096
tlv5636 2.7 v to 5.5 v low power 12-bit digital-to-analog converter with internal reference and power down slas223 june 1999 10 post office box 655303 ? dallas, texas 75265 typical characteristics figure 12 4.0 3.0 2.0 1.0 0.0 1.0 2.0 3.0 4.0 0 4096 inl integral nonlinearity lsb digital input code integral nonlinearity vs digital input code 1024 2048 3072 application information general function the tlv5636 is a 12-bit, single supply dac, based on a resistor string architecture. it consists of a serial interface, a speed and power-down control logic, a programmable internal reference, a resistor string, and a rail-to-rail output buffer. the output voltage (full scale determined by reference) is given by: 2ref code 0x1000 [v] where ref is the reference voltage and code is the digital input value in the range 0x000 to 0xfff. a power on reset initially puts the internal latches to a defined state (all bits zero). serial interface the device has to be enabled with cs set to low. a falling edge of fs starts shifting the data bit-per-bit (starting with the msb) to the internal register on high-low transitions of sclk. after 16 bits have been transferred or fs rises, the content of the shift register is moved to the dac latch, which updates the voltage output to the new level. the serial interface of the tlv5636 can be used in two basic modes: four wire (with chip select) three wire (without chip select) using chip select (four-wire mode), it is possible to have more than one device connected to the serial port of the data source (dsp or microcontroller). figure 13 shows an example with two tlv5636s connected directly to a tms320 dsp.
tlv5636 2.7 v to 5.5 v low power 12-bit digital-to-analog converter with internal reference and power down slas223 june 1999 11 post office box 655303 ? dallas, texas 75265 application information serial interface (continued) tms320 dsp xf0 clkx dx fsx xf1 tlv5636 cs fs din sclk tlv5636 cs fs din sclk figure 13. tms320 interface if there is no need to have more than one device on the serial bus, then cs can be tied low. figure 14 shows an example of how to connect the tlv5636 to tms320, spi ? or microwire ? using only three pins. tms320 dsp fsx clkx dx tlv5636 sclk din fs spi i/o sck mosi tlv5636 sclk din fs microwire i/o sk so tlv5636 sclk din fs cs cs cs figure 14. three-wire interface notes on spi ? and microwire ? : before the controller starts the data transfer, the software has to generate a falling edge on the i/o pin connected to fs. if the word width is 8 bits (spi ? and microwire ? ), two write operations must be performed to program the tlv5636. after the write operation(s), the dac output is updated automatically on the 16 th positive clock edge. serial clock frequency and update rate the maximum serial clock frequency is given by: f sclkmax 1 t whmin t wlmin 20 mhz the maximum update rate is: f updatemax 1 16 t whmin t wlmin 1.25 mhz note that the maximum update rate is just a theoretical value for the serial interface, as the settling time of the tlv5636 has to be considered, too.
tlv5636 2.7 v to 5.5 v low power 12-bit digital-to-analog converter with internal reference and power down slas223 june 1999 12 post office box 655303 ? dallas, texas 75265 application information data format the 16-bit data word for the tlv5636 consists of two parts: program bits (d15..d12) new data (d11..d0) d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 r1 spd pwr r0 12 data bits spd: speed control bit 1 fast mode 0 slow mode pwr: power control bit 1 power down 0 normal operation the following table lists the possible combination of the register select bits: register select bits r1 r0 register 0 0 write data to dac 0 1 reserved 1 0 reserved 1 1 write data to control register the meaning of the 12 data bits depends on the selected register. for the dac register, the 12 data bits determine the new dac output value: data bits: dac d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 new dac value if the control register is selected, then d1, d0 of the 12 data bits are used to program the reference voltage: data bits: control d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x x x x x x x ref1 ref2 x: don't care ref1 and ref0 determine the reference source and, if internal reference is selected, the reference voltage. reference bits ref1 ref0 reference 0 0 external 0 1 1.024 v 1 0 2.048 v 1 1 external caution: if external reference voltage is applied to the ref pin, external reference must be selected.
tlv5636 2.7 v to 5.5 v low power 12-bit digital-to-analog converter with internal reference and power down slas223 june 1999 13 post office box 655303 ? dallas, texas 75265 application information example: set dac output, select fast mode, select internal reference at 2.048 v: 1. set reference voltage to 2.048 v (control register): d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 2. write new dac value and update dac output: d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 0 new dac output value the dac output is updated on the rising clock edge after d0 is sampled. to output data consecutively using the same dac configuration, it is not necessary to program the control register again. linearity, offset, and gain error using single ended supplies when an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. with a positive offset, the output voltage changes on the first code change. with a negative offset, the output voltage may not change with the first code, depending on the magnitude of the offset voltage. the output amplifier attempts to drive the output to a negative voltage. however, because the most negative supply rail is ground, the output cannot drive below ground and clamps the output at 0 v. the output voltage then remains at zero until the input code value produces a sufficient positive output voltage to overcome the negative offset voltage, resulting in the transfer function shown in figure 15. dac code output voltage 0 v negative offset figure 15. effect of negative offset (single supply) this offset error, not the linearity error, produces this breakpoint. the transfer function would have followed the dotted line if the output buffer could drive below the ground rail. for a dac, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after offset and full scale are adjusted out or accounted for in some way. however, single supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. so the linearity is measured between full-scale code and the lowest code that produces a positive output voltage.
tlv5636 2.7 v to 5.5 v low power 12-bit digital-to-analog converter with internal reference and power down slas223 june 1999 14 post office box 655303 ? dallas, texas 75265 application information power-supply bypassing and ground management printed-circuit boards that use separate analog and digital ground planes offer the best system performance. wire-wrap boards do not perform well and should not be used. the two ground planes should be connected together at the low-impedance power-supply source. the best ground connection may be achieved by connecting the dac agnd terminal to the system analog ground plane, making sure that analog ground currents are well managed and there are negligible voltage drops across the ground plane. a 0.1- m f ceramic-capacitor bypass should be connected between v dd and agnd and mounted with short leads as close as possible to the device. use of ferrite beads may further isolate the system analog supply from the digital power supply. figure 16 shows the ground plane layout and bypassing technique. 0.1 m f analog ground plane 1 2 3 4 8 7 6 5 figure 16. power-supply bypassing definitions of specifications and terminology integral nonlinearity (inl) the relative accuracy or integral nonlinearity (inl), sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors. differential nonlinearity (dnl) the differential nonlinearity (dnl), sometimes referred to as differential error, is the difference between the measured and ideal 1 lsb amplitude change of any two adjacent codes. monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. zero-scale error (e zs ) zero-scale error is defined as the deviation of the output from 0 v at a digital input value of 0. gain error (e g ) gain error is the error in slope of the dac transfer function. total harmonic distortion (thd) thd is the ratio of the rms value of the first six harmonic components to the value of the fundamental signal. the value for thd is expressed in decibels. signal-to-noise ratio + distortion (s/n+d) s/n+d is the ratio of the rms value of the output signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for s/n+d is expressed in decibels.
tlv5636 2.7 v to 5.5 v low power 12-bit digital-to-analog converter with internal reference and power down slas223 june 1999 15 post office box 655303 ? dallas, texas 75265 spurious free dynamic range (sfdr) spurious free dynamic range is the difference between the rms value of the output signal and the rms value of the largest spurious signal within a specified bandwidth. the value for sfdr is expressed in decibels. effects of negative offset error for single supply devices to be added here.
tlv5636 2.7 v to 5.5 v low power 12-bit digital-to-analog converter with internal reference and power down slas223 june 1999 16 post office box 655303 ? dallas, texas 75265 mechanical data d (r-pdso-g**) plastic small-outline package 14 pins shown 4040047 / d 10/96 0.228 (5,80) 0.244 (6,20) 0.069 (1,75) max 0.010 (0,25) 0.004 (0,10) 1 14 0.014 (0,35) 0.020 (0,51) a 0.157 (4,00) 0.150 (3,81) 7 8 0.044 (1,12) 0.016 (0,40) seating plane 0.010 (0,25) pins ** 0.008 (0,20) nom a min a max dim gage plane 0.189 (4,80) (5,00) 0.197 8 (8,55) (8,75) 0.337 14 0.344 (9,80) 16 0.394 (10,00) 0.386 0.004 (0,10) m 0.010 (0,25) 0.050 (1,27) 0 8 notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). d. falls within jedec ms-012
tlv5636 2.7 v to 5.5 v low power 12-bit digital-to-analog converter with internal reference and power down slas223 june 1999 17 post office box 655303 ? dallas, texas 75265 mechanical data dgk (r-pdso-g8) plastic small-outline package 0,69 0,41 0,25 0,15 nom gage plane 4073329/b 04/98 4,98 0,25 5 3,05 4,78 2,95 8 4 3,05 2,95 1 0,38 1,07 max seating plane 0,65 m 0,25 0 6 0,10 0,15 0,05 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion. d. falls within jedec mo-187
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (acritical applicationso). ti semiconductor products are not designed, authorized, or warranted to be suitable for use in life-support devices or systems or other critical applications. inclusion of ti products in such applications is understood to be fully at the customer's risk. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 1999, texas instruments incorporated

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